Universal Journal of Electrical and Electronic Engineering Vol. 7(4), pp. 242 - 261
DOI: 10.13189/ujeee.2020.070403
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Translating Hierarchical Simulink Applications to Real-time multi-core Execution

Asma Rebaya ¹, Karol Desnos ^2,*, Salem Hasnaoui ^3
1 SYSCOM Research Laboratory National School of Engineering of Tunis University of Tunis El Manar, Tunisia
² IETR, INSA Rennes CNRS UMR 6164, UEB Rennes, France
³ SYSCOM Research Laboratory, National School of Engineering of Bizerte Carthage University, Tunisia

ABSTRACT

Matlab & Simulink is is widely used as a defacto standard to design industrial applications, video coding & decoding, and signal processing applications. However, with the spectacular increase in the number of the cores available in hardware platforms over these last years, passing from Simulink to multi-core execution becomes more and more complex. In this context, several researches are done to take benefit from the high degree of parallelism and to perform multi-core programming of Simulink applications. In this paper, we present an automated method for transforming hierarchical Simulink applications to embedded parallel software implementation. Our method consists of using IBSDF (Interfaced based Synchronous Dataflow) as an intermediate representation to extract parallelism. Moreover, our approach permits preserving synchronous semantics and hierarchical behavior of the Simulink model. The model-based approach makes it possible to verify the key properties of the system at compile-time, such as deadlock freeness and memory boundedness. The method has been implemented as an extension of the rapid prototyping tool named Preesm. Experiments show that our proposal gives, as a transformation result, a schedulable IBSDF graph equivalent in size to the Simulink model and allows better multi-core implementation performance than Matlab & Simulink sequential execution.

KEYWORDS
Matlab & Simulink Models, Hierarchy, Parallelism, Multi-core Architecture, Rapid Prototyping, Code Generation

Cite This Paper in IEEE or APA Citation Styles
(a). IEEE Format:
[1] Asma Rebaya , Karol Desnos , Salem Hasnaoui , "Translating Hierarchical Simulink Applications to Real-time multi-core Execution," Universal Journal of Electrical and Electronic Engineering, Vol. 7, No. 4, pp. 242 - 261, 2020. DOI: 10.13189/ujeee.2020.070403.

(b). APA Format:
Asma Rebaya , Karol Desnos , Salem Hasnaoui (2020). Translating Hierarchical Simulink Applications to Real-time multi-core Execution. Universal Journal of Electrical and Electronic Engineering, 7(4), 242 - 261. DOI: 10.13189/ujeee.2020.070403.