Universal Journal of Electrical and Electronic Engineering Vol. 2(2), pp. 59 - 69
DOI: 10.13189/ujeee.2014.020203
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Intelligent Custom Block Generation

Michael F. Dossis ^*
Department of Informatics Engineering, Technological Educational Institute of Western Macedonia, Kastoria Campus, Kastoria, 52 100, Greece

ABSTRACT

The current density of integration circuits, yields extremely complex Systems-on-a-Chip (SoCs) that take a long time to design and develop and thus, many times, they miss the market window for these products. This has motivated intensive research on High-level Synthesis (HLS) methodologies, so that such complex and custom systems are rapidly designed and prototyped. The contribution of this work is a formal and intelligent HLS synthesis and rapid verification methodology with custom options, which re-uses and incorporates the generation of predesigned custom hardware functional units, from behavioural ADA code. The usability of the proposed methodology is confirmed with a number of HLS benchmarks including a hierarchical RSA crypto-processor design and a line-drawing algorithm from computer graphics.

KEYWORDS
Custom Hardware Synthesis/Compilation, High-level Synthesis, Hardware Verification, Design Automation, Formal Methods, Intelligent Systems

Cite This Paper in IEEE or APA Citation Styles
(a). IEEE Format:
[1] Michael F. Dossis , "Intelligent Custom Block Generation," Universal Journal of Electrical and Electronic Engineering, Vol. 2, No. 2, pp. 59 - 69, 2014. DOI: 10.13189/ujeee.2014.020203.

(b). APA Format:
Michael F. Dossis (2014). Intelligent Custom Block Generation. Universal Journal of Electrical and Electronic Engineering, 2(2), 59 - 69. DOI: 10.13189/ujeee.2014.020203.