A Detailed Illustration of VLSI Block Design Implementation Process Using VIVADO HLS and Arty Kit

This paper aims to provide consolidated procedure to design and implement VLSI block in Arty A7 kit using VIVADO HLS. Sine wave signal with appropriate pulse width is implemented and default hardware part is selected in VIVADO HLS tool and verilog code has been written in VIVADO IDE for the implementation of Arty A7 kit. Using high level synthesis, an engineer has the contingency to add libraries for the corresponding project and further proceeds with the achievement at superior level of entrancement. The procedure of implementing sinusoidal signal and the performance of implementation in Arty A7 kit using vivado HLS is illustrated along with simulation, synthesis, implementation results and project summary report. Timings, Design rule check (DRC) violations, utilization, total on-chip power are charted in project summary report. The proposed research work is based on FPGA implementation based image compression/decompression using VIVADO HLS. Proposed work is widely used in medical application especially in telehealth where patient records are transferred from remote area to the hospital to make consultation in easier manner. Likewise FPGA implementation based image compression/ decompression is used in fields like remote sensing, oceanography, earth observation etc. to predict the future weather conditions and it helps to take precautionary steps in order to detect the disaster before it occurs. Initial proposed research work has been done based on FPGA implementation of sinusoidal signal using VIVADO HLS. Future research work, FPGA implementation based image compression/decompression will be carried out using VIVADO HLS. The main advantage of Vivado HLS tool is to obtain high speed performance and low power consumption while implementing in hardware.

Abstract This paper aims to provide consolidated procedure to design and implement VLSI block in Arty A7 kit using VIVADO HLS. Sine wave signal with appropriate pulse width is implemented and default hardware part is selected in VIVADO HLS tool and verilog code has been written in VIVADO IDE for the implementation of Arty A7 kit. Using high level synthesis, an engineer has the contingency to add libraries for the corresponding project and further proceeds with the achievement at superior level of entrancement. The procedure of implementing sinusoidal signal and the performance of implementation in Arty A7 kit using vivado HLS is illustrated along with simulation, synthesis, implementation results and project summary report. Timings, Design rule check (DRC) violations, utilization, total on-chip power are charted in project summary report. The proposed research work is based on FPGA implementation based image compression/decompression using VIVADO HLS. Proposed work is widely used in medical application especially in telehealth where patient records are transferred from remote area to the hospital to make consultation in easier manner. Likewise FPGA implementation based image compression/ decompression is used in fields like remote sensing, oceanography, earth observation etc. to predict the future weather conditions and it helps to take precautionary steps in order to detect the disaster before it occurs. Initial proposed research work has been done based on FPGA implementation of sinusoidal signal using VIVADO HLS. Future research work, FPGA implementation based image compression/decompression will be carried out using VIVADO HLS. The main advantage of Vivado HLS tool is to obtain high speed performance and low power consumption while implementing in hardware.

Introduction
VIVADO IDE (Integrated Developed Environment) contributes perspective graphics user interface (GUI) along extraordinary features. Restraint practices will be carried out during entire design process. Timing analysis can be done after power estimations, synthesis, and placement and routing. Modifications are done for the designs accordingly in real time, instead of going for re-implementation. The VIVADO Design Suite with an emphasis on the different project types, using the tool through the GUI and TCL, with a project and without. VIVADO IDE includes, Register Transfer Level design languages used are VHDL, Verilog and System Verilog, IP catalog, Performing Behavioral, functional, timing simulation using vivado simulator, Synthesis design, Optimized Implementation design, Serial input and output ports, Logic analyzer for debugging, Power and Timing analysis, SDC based xilinx design constraints, Floor planning in higher level, Detailed Placement and Routing, Bitstream configuration and Generation. VIVADO adopts an approach of viewing design arrangement in memory. Viewing an arrangement leads to create a design netlist for the appropriate design flow, it allots design constraints to the particular design arrangement and after that dumping the particular design to the targeted equipment. This feature contributes capability of viewing and considering the designs at each phase and it can be done with various implementation methods with retuned timing constraints. Hardware functions are synthesized into 202 A Detailed Illustration of VLSI Block Design Implementation Process Using VIVADO HLS and Arty Kit hardware in the Programmable Logic (PL) by the VIVADO HLS compiler. This compiler automatically translates C/C++ code into an FPGA hardware implementation, and as with all compilers, using compiler defaults. There are two flows for optimizing the hardware functions. Top-down flow: In this flow, program decomposition into hardware functions proceeds top down within the SDSoC environment, letting the system compiler create pipelines of functions that automatically operate in dataflow mode. The microarchitecture for each hardware function is optimized using VIVADO HLS. Bottom-up flow: In this flow, the hardware functions are optimized in isolation from the system using the VIVADO HLS compiler provided in the VIVADO Design suite. The hardware functions are analyzed, optimizations directives can be applied to create an implementation other than the default, and the resulting optimized hardware functions are then incorporated into the SDSoC environment. To perform optimizations using VIVADO HLS, it consists of directives which specify a methodology how optimizations are applied in a deterministic and efficient manner. Bottom-up flow is often used in organizations where the software and hardware are optimized by different teams and can be used by software programmers to take advantage for hardware implementations. Both flows are supported and results in the same high-performance system. Xilinx sees the choice as a workflow decision made by individual teams and organizations and provides no recommendation on which flow to use.

Literature Review
Marcin kowalczyk et al [1] [12] [15] [17] explains about hardware implementation preferred for contingent based image pre-processing sections for a 3840x2160 at 60fps video stream in a Zynq UltraScale and MPSOC is explained. Successive processes like simple averaging, Gaussian filter, Edge detection using SOBEL and CANNY methods, median filter and morphological erosion and dilation are undergone. Video stream is considered in the pattern of 2 and 4 pixels per clock. Logic methods are characterized in VHDL code using high level synthesis tool, VIVADO HLS. Elaborated segments backing real time processing of 4k at 60fps video stream. The above concept clearly states that employment of computations with lower clock frequency acquires clear development on energy utilization against increment in the count of utilized logic resources. Bhaumik vaidya et al [5] [3] [14] [16] describes about effective implementation results for discrete image processing algorithms using VIVADO HLS. FPGA kits like virtex 7, virtex 6, Spartan 6 are utilized to give comparative implementation results. Parameters considered are speed, latency and resource utilization. Basic image processing algorithms like evaluation of histogram, histogram equalization, averaging filter and laplacian filter are selected to produce complete kit expedition for using VIVADO HLS. This process starts from dumping high level C/C++/System C Code in FPGA kits mentioned above using VIVADO HLS is elucidated or described including implementation results for different image processing algorithms. Ajay Rupani et al [4] [7] [13] discusses about image processing has been done by coordinating raspberry-PI and FPGA using IOT. IOT means Internet of Things, which widen the connectedness of substantial equipment and usual gadgets. IOT plays a vital role in day to day life. Image processing followed by image filtering also done by using above mention interfacing. The mode of process has been carried out by using ZEDBOARD ZYNQ 7000 FPGA and raspberry-PI. Image filtering process like Gaussian filter, sharpening filter and average filter, edge detection and gray scale operations are also done and the results are visualized using VGA monitor. Usage of chip is indicated. A.cortes et al [12] [9] [11] explains about image processing algorithms are constructed in Zynq SOC using VIVADO HLS and are matched with mandated architectures. In VIVADO HLS, an engineer has a scope to add library files to open CV, an open CV is extensively used by the software designers. Here is the process is explained in view of area resources with library files and without library files. This case study is about data binning, a step row filter and sobel filter. The above algorithms are very common in image processing filed so they are adopted for above process. In VIVADO HLs tool, excluding of library files, there is a reduction in time for whole process. On the other hand, including of the library files it increases the FPGS resources i.e. area. Ghislain Takam Tchendjou et al [6] [2] [10] evaluate the functions of machine learning techniques for the technique, image quality assessment.
Here the proposed methods are divided into two classifications (linear discriminant analysis and k-nearest neighbors) and four non-linear regressions accesses (artificial neural network, non-linear polynomial regression, decision tree and fuzzy logic). Establishment and the vitality of the architecture of calculated by applying (monte-carlo cross validation), with inconstantly 1000 verification sets. Simulation results determine the fuzzy logic method which has largest reliable approach and better optic opinion. Implemented methods produces ultimate fuzzy logic modeling employing Gaussian and derived membership functions. The proposed implementation is carried out on Kintex 7 FPGA kit with Xilinx VIVADO HLS tool.

Proposed Work
The Proposed research work focuses on describing about the performance results like simulation, synthesis, implementation and generating project summary report and verilog implementation of Arty A7 kit using xilinx Universal Journal of Electrical and Electronic Engineering 7(3): 201-208, 2020 203 VIVADO HLS tool. Work starts by creating a RTL project, Here you will be able to add sources, create block designs in IP integrator, generate IP, run RTL analysis, synthesis, implementation, design planning and analysis. Then add sources and constrains, set the target language as Verilog and simulator language as "mixed". Then choose default part or board for your project, this can be changed later. After adding all those things, a new project summary will be displayed then click Finish, a new project will be created. After creating a new project, project settings have to be done. In VIVADO IDE, click on flow navigator, project manager with wide variety of options like settings, IP catalog, IP integrator, simulation, RTL analysis, synthesis, implementation, program and debug are displayed. Steps to be performed for project settings, Click on settings under project manager. Here options with project settings and tool settings are displayed. In tool settings, choices like text editor, web talk, color, strategies, window behavior are listed these options are default options there won't be any changes made here. In project settings, tabs like general, simulation, elaboration, synthesis, implementation, bit stream, IP are listed. In general tab, specify values for various settings used throughout the design flow. These settings are applied to the current project. Settings like project device, target language as "Verilog", default library file, top module name. Language options like loop count are displayed default. In simulation tab, specifies various settings like target simulator as "VIVADO simulator", simulator language as "Mixed", simulation set as SIM1 and simulation top module name. Then in compilation and elaboration check the library files, in simulation give run time as 1000 ns, in netlist set the process as "Slow" and in advanced tab, enable incremental compilation it preserves simulation files during successive simulation runs. In elaboration tab, specifies various settings associated to elaboration like LINK IP model options as "netlist model" and constrains options as "Load constrains". In synthesis, it specifies various settings like default constraint sets as CONSTRS1. Strategy will display the VIVADO synthesis default reports. In synthesis description, default stated as higher performance designs, resource sharing is turned off, the global fan out guide is set to a lower number, FSM extraction forced to one-hot, LUT combining is disabled, equivalent registers are preserved, SRL are inferred with the larger threshold. In implementation, settings like constrains and report options are indicated. Default options like design initialization, opt design, power opt design, place design, post-place power opt design, post-place phy opt design, route design, post route phy op design are enabled. In bit stream tab, settings are related to writing bit stream, here (-bin_file*) is enabled. In IP tab, enabled pre compiled IP simulation libraries, automatically generate simulation scripts for IP, generate log file. IP location where output products and customization are stored. IP cache set us "local". After finishing all these settings, click on Apply and OK. Complete project settings are done to the newly created project. Now move on to give the input signal as "sine wave" signal. Click on IP catalog under flow navigator, a separate window with cores and interfaces are opened in that type "DDS COMPILER" selects the core as wave form synthesis  DDS compiler  AXI4-stream  production  version 6.0.

IMPLEMENTATION OF ARTY A7 KIT USING VIVADO TOOL:
In VIVADO IDE, Click on add sources and add or create design sources then click on next and create file with file name as verilog file (.v file), then click on finish now the IDE environment has been opened for hardware implementation. Verilog code has been written for implementation with input signal as 'CLOCK' and output signal as 'LED' then the register count as [24:0] are adopted. By incrementing the register count value LED will blink accordingly. Run simulation, synthesis, and implementation.
After implementation, bitstream generation will be completed (.bit file) has been generated accordingly. Now click on "Open hardware manager" then "open target" it will interface the Arty A7 kit and VIVADO tool along with the connection of local host. Then the implementation result can be viewed by blinking of "LED" light.

Results
Simulation result Figure 1. Simulation result using VIVADO for Arty A7 kit Click on simulation  run behavior simulation. Simulation scripts are generated and also it will generate simulation wave form for the given input according to the phase width and output width values. Output simulation waveforms from 0 to 1000 ns are displayed above. Right click on synthesis run synthesis  launch synthesis run and click OK in dialog box for starting synthesis. It will take time to perform, synthesis scripts are generated and the designs are produced accordingly which is displayed above. Figure 3. Schematic view using VIVADO for Arty A7 kit Schematic view  Click on open schematic view and click OK in dialog box for starting the implementation, it will take time to perform, schematic view of the design will be displayed as shown above. Figure 4. Implementation design using VIVADO for Arty A7 kit Right click on implementation  run implementation  launch implementation run and click OK in dialog box for starting the implementation, it will take time to perform, here route_design will be completed after implementation process which is shown above. Elaborated design  Click on open elaborated design and click OK in dialog box for starting the implementation, it will take time to perform and elaborated design will be displayed as shown above. Figure 6. Generation of bitstream file using vivado for Arty A7 kit

Project summary report
Project summary report has been generated along the details with settings, board part, synthesis, implementation, DRC violations, timing, utilization, power screenshots are displayed below.

Conclusions
The above procedure shows that design and implementation using VIVADO HLS has been done in Arty A7 kit. Results for simulation, synthesis design, implementation design, schematic view, and bitstream generation, block design, snapshot for implementation Arty A7 kit are illustrated. Project summary report along with board part is indicated. RTL design (or) RTL implementation has an advantage of both time consuming and error prone. The main advantage of using VIVADO HLS, improves the design in better way, decreases device resource utilization and latency with increased throughput.