Quantum Effects Investigation in 20 nm Gate Underlap SOI MOSFET for Millimeter Wave Applications

This paper presents the investigation of quantum effects of gate underlap 20nm Silicon-On-Insulator (SOI) MOSFETs at 60 GHz. At optimized spacer s = 0.8LG with doping gradient d = 5nm/decade the device DC and AC performances have been investigated with and without quantum effects. After incorporation of quantum effects, at 60 GHz the device current gain, unilateral gain (ULG) and device intrinsic gain are found 50 dB, 70 dB and 36dB respectively at power consumption 0.6 mW. All these parameters have been extracted using 2D ATLAS device simulator. The average 50% performance of device has been increased after incorporating quantum effects model. Although simulated result for current gain nearly 25% higher than measured data (gate length LG = 20nm) whereas for transit frequency fT is differ (>13%). However, these comparisons with limited measured data suggest the possibility of use of this device technology in the design of key blocks like low noise amplifier (LNA) and Mixer for mm-w applications.


Introduction
In the past few years, low-power low-voltage silicon-on insulator (SOI) MOSFET technology has emerged as a leading candidate for highly integrated circuits for wireless applications [1]. However, below the 20 nm technology node, upcoming CMOS technologies face many technological challenges, the most crucial being the short channel effects (SCEs) that tend to degrade sub threshold characteristics and increase leakage current because of quantum effects [2]. The influence of film-thickness reduction on the threshold voltage of single and double-gate SOI MOSFETs has been reported in the literature [3]. It is found that, due to quantum confinement of carriers in a thin silicon layer, the minimum energy for electrons in the conduction band increases when the thickness of the silicon film is reduced [4]. As a result, the threshold voltage increases as the film thickness is reduced. This effect was first predicted by Omura et al. in 1993, and has been simulated and observed experimentally by several groups since [5]. It is included in modern thin-film SOI and double-gate MOSFET simulators [6].
In this paper, we report a similar effect in n-channel single gate underlap fully depleted SOI MOSFETs. The threshold voltage increases when the cross section of the device is decreased-due to quantum-confinement effects. Furthermore, the minimum energy for the electrons in the conduction energy sub-bands increases with the electron concentration, which dynamically increases the threshold voltage as the inversion charge builds up [7][8]. This effect reduces the current drive of the device and is not predicted by classical simulators. That's for solving such a problem we need to add a self-consistent Poisson-Schrödinger solver for more explanation about that has been given in section-2. The effects of quantum at high frequency (> 60 GHz) has been observed and discussed in section-4.

What is Quantum Effects?
To adequately predict quantum effects due to the formation of energy sub bands, it is necessary to solve the Poisson equation and the Schrödinger equation self-consistently [9]. The Poisson equation is given by.
in the silicon and the silicon dioxide Where m * ds is the density-of-states electron mass, and E j and Ψ j are the minimum energy and the wave function of the j th sub band, respectively. The density-of-states electron mass is defined by * = 6 2 3 ( * 2 * ) 1/3 = 1.08 0 where * and * are the transverse and longitudinal electron masses in athree-dimensional (3-D) silicon crystal [10][11]. Different mass values can be used to describe more accurately devices made along particular crystal orientations [12], but the general results and conclusions presented here are qualitatively applicable to any orientation. The Schrödinger equation is solved both in the silicon and the silicon dioxide, with boundary conditions insuring the continuity of the wave functions at the Si/SiO 2 interfaces. The electron concentration is obtained by adding the electron concentrations of all sub bands. Since sub bands located at an energy more than 10 kT above the minimum of the conduction band have a negligible electron population, we confine the calculation of the electron density to energies ranging from EC to EC + 10 kT. The electron concentration is thus given by [12] n (x,y) where ( ) is the density of states in the j th sub band ( ) is the Fermi-Dirac distribution function. The density of states used in the simulations corresponds to that of a one dimensional structure [13].
Where is the cross-sectional area of the silicon film. The Fermi-Dirac distribution is given by the familiar expression.
Since only sub-bands with energy less than 10 kT above the minimum of the conduction band are populated with a significant number of electrons, the number of sub bands N used in each calculation is limited and can be calculated from the silicon cross-sectional area and the temperature. The following expression is used to calculate the discrete integer of bands [13].
A cross section of the simulated device and the number of sub-bands corresponding to a MOSFET with square cross section (i.e., the silicon width W is equal to the silicon thickness T si ). The Poisson equation is first solved with n(x, y) = 0 as initial condition. The resulting potential distribution is fed into the Schrödinger equation to calculate the two-dimensional (2-D) wave functions and their energy levels. Using this information, the electron concentration n(x, y) is calculated using (4). The electron concentration is then introduced in the Poisson equation and a Newton-Raphson iteration process is used until convergence of the electron concentration is obtained. The criterion for convergence is a variation of electron concentration less than 0.1% between two iterations.

Device under Study
At mm-w frequencies, the device optimization has a significant impact on importance of the overall performance.As a result, careful device design becomes quite important in pushing the capability of nano-scale SOI to higher GHz range (>10GHz). This section describes the device design intended to optimize the device physical structure in terms of spacer width s and doping gradient d as shown in Fig. 1a. Device structure comprises of a gate length L G =20nm, gate oxide thickness tox = 1.5nm and buried oxide thickness t box = 106.5 nm. The p-type doping used on SOI layer has doping equal to10 16 cm -3 for adjusting a low value of threshold voltage V TH = 0.26V, which is required for low power applications. The undoped device (Fig. 1a) with mid band metal gate work function equal to 4.72 eV has been simulated using 2D ATLAS simulator [14].This device has been optimized to simultaneously maximize the transit frequency f T and voltage gain A v and corresponding values for s and d, which has been found equal to 0.8×L G and 5nm/decade, respectively [6].In order to keep the device almost free from short channel effect, the natural length ( 1 = [16]. The doping gradient of the designed device along cut line in the channel region is shown in Fig.1b. The optimal underlap profile for better analog/RF performance is obtained with spacer to straggle ratio s/σ = 4 is used.

Results Analysis
Quantum effects in underlap SOI MOSFET has been observed for millimeter wave applications. A self-consistent Poisson-Schrödinger solver is used to solve the quantum effects. In Table-1 the data are tabulated the performance of device before and after adding quantum effects model. Fig-2a shows that drain current has been increased after adding the quantum model and has become 0.575 mA but before addition of quantum model it is a 0.05 mA this increment of current is due to use of quantification effects inside the channel and movement of electron inside the channel ballistic not drift -diffusive .  From Fig-3a and 3b it can be concluded that transconductance gm and output conductance g ds of device is constant up to frequency of interest 60 GHz and also it maintains the intrinsic gain of device 36dB. The most important figure of merit of MOSFETs at millimeter wave frequencies is the current gain (|H 21 |), which is given by [17][18] The unilateral gain (ULG) is defined as the maximal available gain of a device when the stability is ensured by using a lossless feedback network to cancel the reverse transmission of the device. From the different gain expressions defined above, it is possible to introduce two important figures-of merit: the cut-off frequency of the current gain (f T ) and the cutoff frequency of the maximum power gain also referred to as the maximum oscillation frequency (f MAX ). f T is extracted as the frequency at which short-circuit current gain |H21| becomes equal to unity or 0 dB. Considering the simplified small signal equivalent circuit presented in Fig. 5 f T can be approximated by the following relation. ≅ + (9) Note that f T is only dependent on the intrinsic parameters of the MOSFET. Then it is an important factor to compare different technologies and devices, fT, measure the intrinsic bandwidth of the device. The maximum frequency of oscillation f MAX is defined as the frequency for which the unilateral gain (ULG) becomes equal to unity or 0 dB and approximated by following relation [10]: Fig . 4a and 4b shows the current gain and unilateral gain before and after adding the quantum effects and it has been found that approximately the value of current gain and unilateral gain after adding quantum effect has become just double.   Fig.4c shows the plot of fT and fMAX which is extracted by 2D ATLAS simulator [14] and for authentication of data these extracted results has been compared with measured data [6] and found nearly 13% increased.

Conclusions
The enormous potential of source drain extension region engineering in 20 nm SOI MOSFETs for millimeter wave applications has been extensively analyzed for 20 nm gate length. A self-consistent Poisson-Schrödinger solver was used to calculate the current in n-channel SOI transistors. The minimum energy of the subbands and the threshold voltage increase as the cross-sectional area of the device was reduced and as the electron concentration in the channel was increased. As a consequence, the threshold voltage was higher than predicted by classical Poisson Solvers. It has been found that the presence of optimal spacer length s = 0.8L G does not degrade the performance of device. This optimal spacer reduces feedback capacitance sufficiently to enhance intrinsic gain of device as well as both f T and fMAX. It has been observed from results that after adding quantum effects 50% performance of device has been increased. The device is maintained the current gain and ULG 50 and 70 dB respectively with power consumption 0.6mW. So these results suggest the suitability of this technology to design of mm-w front end key blocks like low noise amplifier (LNA) and Mixer.

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Quantum Effects Investigation in 20 nm Gate Underlap SOI MOSFET for Millimeter Wave Applications