Design of Linear CMOS Transconductance Elements for Alpha-Power Law Based Mosfets and an Automatic Compensation Technique for Temperature

A model on alpha-power law MOSFETs based source-coupled differential pair (SCDP) is discussed and a simple design procedure for realizing a linear CMOS SCDP transconductance element is proposed. The proposed or modified SCDP circuit using this procedure is an alternative to that of conventional SCDP and the circuit discussed has superior linearity for a wide range ±(0-300mv) of input differential voltage at a supply voltage of 1.2v. The modified SCDP also includes the circuitry needed to suppress the variation in the quiescent current with respect to input common-mode voltage noise. The SPICE results are used to verify theoretical predictions. The results show close agreement between the predicted model behavior and the simulated performance. The simulated result on Total Harmonic Distortion (THD) shows that the modified SCDP circuit is better than the conventional SCDP by about four times at input differential voltage amplitude of ±100mv. An example circuit, a second order continuous time gm-C band-pass filter is constructed using the fully differential modified SCDP and the fully differential conventional SCDP circuit and the result shows that the modified transconductor circuit is better in linearity (THD) than the conventional SCDP by about two times at the input differential voltage amplitude of ±100mv. An automatic digital compensation scheme for temperature is also presented and the temperature coefficient of output current is reduced by about eight times to 250ppm/deg.C after compensation for the maximum change in temperature of 150deg.C and at the input differential voltage of 100mv.


Introduction
Linear transconductance elements [1]- [14] are useful in building blocks in analog signal-processing systems and the literature on this topic is rich indeed. A cross-coupled quad cell is proposed by [1]. An inverter-based transconductor is discussed in [10] and [13]. In [9], a bias-offset cross-coupled transconductor is realized. In [1] and [8], the linearity with input differential voltage is achieved by CMOS pairs and floating voltage sources. In [6], the linearity is achieved with two additional PMOS SCDP pairs. The source degeneration linearization is used in [11]. A four MOS transistor cell to obtain a linear transconductor is realized in [12]. In [14], the linearity is obtained with a quadritail cell. In all of these transconductors discussed, only the square law devices are considered but in the present paper, a model for SCDP based on the alpha-power law devices is proposed.
The objective of this paper is to present a model for the alpha-power law based CMOS SCDP transconductors and a simple design procedure for the realization of linear CMOS modified SCDP transconductance block for both single-ended and fully differential outputs. The modified SCDP doesn't require any special cell and includes the same circuit as required in a conventional SCDP as the base circuitry. Also the linearity and the input voltage range of the proposed design are superior to that of the conventional source-coupled differential pair. The computer simulation results are presented.
All MOSFET's are assumed to be enhancement-mode types biased in saturation and the transistor behavior is approximated by the relation, V -vth 1+λV 2 (1) where vth is the total threshold voltage inclusive of body-effect.
( ) kp=KP W/L is the transconductance parameter, W and L are the width and length of the channel, λ is due to the effect of channel length modulation and α is the alpha-power law value. A theory on modeling a transconductance parameter for a SCDP transconductor based on alpha-power law MOSFETs is described in section-2. A condition to achieve the linearity Universal Journal of Electrical and Electronic Engineering 2(5): 234-244, 2014 235 in the transconductance parameter is discussed in section-3. Section-4 proposes a simple design procedure used to cancel out the third degree term in the transconductance and to make a perfect linear transconductor. The section-4 also includes the circuitry that is needed to minimize the variation of quiescent current with respect to input common-mode voltage. The section-5 presents the results, one with alpha-power law devices and the other with square law devices for both SCDP and the modified SCDP. The section-6 describes on how the various output conductances (channel length modulation) are included in the present model for the fully differential modified transconductor. A gm-C band-pass filter based out of the conventional SCDP and the modified SCDP is described in section-7. Using this filter, a comparison between the conventional SCDP and the modified SCDP in terms of %THD is made in section-7. An automatic temperature compensation scheme for the discussed modified transconductor is also presented in section-8. Section-9 concludes about the modified SCDP circuitry based on alpha-power law MOSFETs.

Theory on Basic Cmos Scdp Transconductor Based on Alpha-Power Law Mosfets
Let 1 I and 2 I be the drain currents in the two branches of the SCDP circuit ( Fig.1) and gs1 V and gs2 V be the gate-source voltages of the respective NMOS MOSFETs in the SCDP. vth is the total effective threshold voltage of NMOS MOSFETs including body-effect. The body-effect's dependence on input differential voltage is considered in section-3. Neglecting channel length modulation for time being (it is accounted later in the section-6), we have from (1) as, Using (2) and (3), we obtain, where Iss is the quiescent current for SCDP.
From (4) and (5) (6) and this could be written using (2) as, Expanding (7) we arrive at, where VX is given by ( ) Let cm V be the input common-mode voltage. P V is the node voltage at the point P in Fig.1 From equations (9), (10) and (11), VX can be written as, where K is given by The differential current D I for a source-coupled pair can be written as, 3 D 0 in 1 in I =a V +a V +(higher order terms) (14) and let biasing current Iss be written as, 2 0 q in Iss=I +m V +(higher order terms) Now consider in equations (8), (12) and (13), we have, Expanding the curly bracket term by binomial series and neglecting higher order terms and noting that the above equation should be equal to 2 Iss since the dc term of equation (14) is zero, we have equation (16) that could be written from equations (8), (12), (13) and (15) Now writing equation (12) by binomial series, we obtain, Substituting equations (20) and (22) in equation (8) we arrive D I after neglecting higher order terms as, Equations (23) and (24) constitute the required equations for the output differential current which are similar to the one in square law based SCDP circuit.

Condition for the Compensated SCDP
The equation (28) shows that the term in the square bracket should be zero to achieve a linear transconductance. This result can be stated as,  Fig.1, P V can be written as, The threshold voltage vth is given approximately by, where 1 K and 2 K are due to non-uniform substrate doping and s Φ is the surface potential. Using equation (33), vth can be written as, 2 2 where S is given by,   Expanding the bracket term in the above equation (35) by binomial series, we obtain after neglecting higher order terms as, where P K is given by, From equations (19), (33) and (37), we have the modified 0 I as, Writing the equation (40) by binomial series, we obtain (after neglecting higher order terms and keeping only the 2 in V term) as, Upon expansion of ( ) m new value by binomial series and neglecting higher order terms, we get the following equation.
Now Iss can be written from using equations (46) and (48) as, The inclusion of P V and vth varying with 2 in V has already been accounted in the second term of above equation (49) and its effect makes explicit presence in the third term of equation (49). The modified ' m ' after neglecting higher order terms can be written as, which is same as the equation (30). The next section discusses on how to achieve the condition (50) to make a perfect linear transconductor.

Design of Modified SCDP with Compensation for Linearity
The modified SCDP circuit with compensation for linearity is shown in Fig.2 and Fig.3. This is exactly the same circuit as the basic SCDP but with a little difference in the biasing circuit.
The ' m ' value can be obtained from the low value of biasing resistor R (Fig.2) where R is the biasing resistor and 1 R is the resistor as shown in Fig.3. out R is the output resistance seen from the point P as shown in Fig.3. s1 V and x V are the fixed potentials as shown in Fig.3. 2 R and x V provide the value of ( x cm V -V ) for equation (51) as per Fig.3. Here 2 R is chosen to be much larger than R and 1 R for reduced power consumption.
From (46) and (52), we find, and 0M P0 P out Note that due to noise voltage changes in cm V , the quiescent current 0M I varies and changes the output common-mode voltage. Without P I current, the low value of R leads to larger variation in 0M I with respect to cm V .
The circuits shown in Fig.2 and Fig.3 provide the value of 0M I with lesser variation with respect to cm V at dc. By differentiating 0M I with respect to cm V in equations (54) and (55) where out C is the output capacitance of the current source block P I seen from the point P as in Fig.3 By substituting (57) in (56), we obtain as, By making 1 R R  , we have 0M I that varies minimally with respect to cm V at dc as shown in equation (58).
A fully differential circuit can be made with two single ended SCDP circuits as shown in Fig.4. The following design procedure steps are required to design a compensated fully differential modified SCDP transconductor.
1. The value of quiescent current ( 0M I ) and kp should be chosen to achieve the transconductance ( m 2G ) for a fully differential circuit (Fig.4) as required for the given design specifications.
2. The biasing resistor ( R ) should be adjusted to provide the required value of ' m ' as in equation (53) for compensation. 3. The value of sourcing current ( P I ) in equation (55) needs to be tuned to provide the required value of 0M I as in equation (54). That is, the potentials s1 V and x V are to be chosen accordingly. Note that in the modified SCDP, the power dissipation is more than the conventional SCDP due to this sourcing current and the opamp's power supply currents as in Fig.3. The current 0M I also varies with the input differential voltage amplitude as per equation (46). If we assume a single sinusoidal input differential voltage of amplitude a V and frequency ω in Fig.2 Note here that the dc value of Iss is changed and is more due to the input differential voltage amplitude. At higher input differential amplitudes, the dc current 0M I is more and this is the reason why two transconductors based fully differential circuit is studied and not a single transconductor based fully differential circuit. In a single transconductor based fully differential circuit, as 0M I increases there is no room to accommodate the increased current, 0M I in M3 and M4 as the gate voltage of these two transistors is fixed (M3 and M4 operate as current sources). Hence, the output common-mode voltage drops due to the channel length modulation effect. In a two transconductors based fully differential circuit (Fig.4), as 0M I increases, the transconductances ( m g ) of M3 and M4 (M3 and M4 are current mirrors) increase and hence the output common-mode voltage tries to maintain approximately at the same level.

Results on Transconductors
The SPICE model library chosen for simulation is 130nm,1.2v, IBM Technology process. There are two examples for a fully differential transconductor shown here, one with alpha-power law characteristic and the other with square law characteristics.  Fig.5 for ideal (straight line), conventional SCDP and modified SCDP circuits.The normalized linearity error in % vs input differential voltage characteristics are given in Fig.6 for both SCDP and modified SCDP circuits.
The transient simulations were performed with a sinusoidal input frequency of 100MHz and an output load capacitance of L C =10pf. The obtained % total harmonic distortion (%THD) Vs input differential voltage amplitude characteristics are shown in Fig.7. It is noted that at higher input voltages the distortion is higher for conventional SCDP than modified SCDP.
A change of 4.42% in quiescent current 0M I is observed for 20mv input common-mode voltage noise at in V =50mv for the fully differential modified SCDP whereas for the fully differential conventional SCDP, the change in 0M Also a change in output common-mode voltage of 6.92% is noticed as the input differential voltage amplitude is changed from in V =10mv to 300mv at input cm V =0.65v for the fully differential modified SCDP whereas for the fully differential single transconductor based conventional SCDP, the change is 62.62% (A high change in output CM voltage!!!). The output noise spectral voltage density at 100MHz for this example-1 transconductor design is 64.7nv/√Hz (for both conventional and modified SCDP) without any output load capacitor. The input referred noise spectral voltage density at 100MHz is 3.4nv/√Hz.  Fig.8 for ideal, conventional SCDP and modified SCDP circuits. Fig.9 shows the normalized errors in % Vs in V characteristics for both SCDP and modified SCDP.
The obtained % THD Vs in V (amplitude) characteristics are shown in Fig.10 for an input frequency of 100MHz and with an output load capacitance of L C =10pf.
For this case, a change of 5.8% in quiescent current 0M I is obtained for 20mv input common-mode voltage noise at in V =50mv for the fully differential modified SCDP whereas for the fully differential conventional SCDP, the change in 0M I is 2.39% .
Also a change in output common-mode voltage of 6.29% is noticed as the input differential voltage amplitude is changed from in V =10mv to 300mv at input cm V =0.65v for the fully differential modified SCDP whereas for the fully differential single transconductor based conventional SCDP, the change is 36.46% (A high change in output CM voltage!!!). For this example-2, the output noise spectral voltage density at 100MHz is 115nv/√Hz for both conventional and modified SCDP circuits without any output capacitor. The input referred noise spectral voltage density at 100MHz is 6.7nv/√Hz.

The Effect of Output Conductances
Consider a fully differential modified SCDP as shown in Fig.4 The output voltage is given by, Substituting equations (65), (66) and (67) in equations (61) and (62), we obtain o V as,

A Second Order Gm-C Bandpass Filter
A second-order continuous time Gm-C bandpass filter is constructed using both fully differential conventional SCDP and modified SCDP circuits. This circuit is shown in Fig.11.
The bulk-node of all the NMOS transistors is tied to ground whereas bulk-node of all the PMOS transistors is tied to Vdd . The input common-mode voltage is chosen as cm V =0.65v. The biasing voltage ( b V ) in the biasing circuit ( Fig.1) is adjusted to provide all the required transconductance values for the case of conventional SCDP.
For modified SCDP, the resistor ( R ) and the current ( P I ) in the biasing circuit ( Fig.2) are adjusted to provide all the wanted transconductances. Any suitable gain ( G ) can be achieved by independently varying m4 G . Figure 11. A second order Gm-C Bandpass Filter using fully differential transconductors The 3dB bandwidth obtained is around 40MHz both for the conventional and the modified SCDP. The transient simulations were carried out for an input frequency of 100MHz with different input differential voltages. The obtained values of total harmonic distortion in % for different input voltage amplitudes are tabulated in Table.1 for both conventional and modified SCDP. Also the power dissipated by the bandpass filter circuit is tabulated in Table.1 for various in V and both for the conventional SCDP and the modified SCDP.
This filter can be operated at any center frequency and the higher frequency limitation is imposed by the sum of bulk-to-drain capacitances ( o C ) of NMOS (M2 or M1) and PMOS (M4 or M3) in the individual transconductors as shown in equations (64) and (68). As long as the sum of load capacitance and the total bulk-to-drain capacitances ( o C ) of M2 and M4 is equal to 1 C or 2 C , the circuit can operate at higher center frequencies. In the present BPF circuit, the circuit operates up to 960MHz as the center frequency.

A Temperature Compensation Scheme for the Modified Transconductor
The various output current versus input differential voltage characteristics for different values of temperature (-50deg.C, 25deg.C and 100deg.C) before compensation and after compensation (as explained below) for the case of example-2 studied in section-5, are shown in Fig.14. A temperature compensation circuit for the modified SCDP is shown in Fig.12. A two 2-bits digital technique has been used to compensate for the temperature above 25deg.C and below 25deg. C just to illustrate for the example-2, discussed in section-5. It is observed that above 25deg.C without temperature compensation, the m G value is lower and hence it requires more quiescent current value for compensation. Below Universal Journal of Electrical and Electronic Engineering 2(5): 234-244, 2014 243 25deg.C, the modified transconductor requires less quiescent current. The Fig.12 is used to provide this adjusted biasing current value based on temperature. The designed values of N R and P R are 11.06k and 58.13k.
The current R I , and hence the drop R V in Fig.13 is used to sense the temperature(T) variation. For the example-2 discussed in section-5, the drop R V varies from 0.440v (-50deg.C) to 0.487v (deg.100C). The designed value of R R is 2.15k. Figure 13. A temperature sensing circuitry for the modified SCDP.
A flash Analog-to-digtal converter (ADC) as shown in Fig.15  For the case of example-2 studied in section-5, the temperature coefficient of output current before compensation is 2081ppm/deg.C at ΔT =150deg.C(maximum), in V =100mv, input cm V =0.65v and 0M I =50uA and the new value of temperature coefficient after compensation is 256ppm/deg.C.
For the example-1 studied in section-5, the temperature coefficient of output current before compensation is 2914ppm/deg.C at ΔT =150deg.C(maximum), in V =100mv, input cm V =0.65v and 0M I =310uA whereas the new value of temperature coefficient after compensation is 563ppm/deg.C.

Conclusions
A theoretical model for a source-coupled differential pair for alpha-power law based MOSFETs has been discussed and a simple design procedure for the circuit compensation technique for realizing a linear SCDP transconductor was proposed. This modified fully differential SCDP has linearity much better than the conventional fully differential SCDP for a wide range of input differential voltages. Also the variation of the quiescent current with respect to input 244 Design of Linear CMOS Transconductance Elements for Alpha-Power Law Based Mosfets and an Automatic Compensation Technique for Temperature common-mode voltage noise was minimized in the proposed design. The output differential voltage dependence on the transistor output conductances has been discussed. An example circuit, a Gm-C bandpass filter has been used to verify linearity in the transconductance value between the fully differential modified SCDP and the fully differential conventional SCDP. An automatic temperature compensation technique for the transconductance value has also been discussed.