A High-Gain and Low-Noise 0.9 μW Operational Amplifier

A low-voltage, low-power, high-gain and low-noise operational transconductance amplifier (OTA) by modifying conventional one is presented and analyzed. Design strategies are discussed for minimizing noise and increasing gain. The simulation results show that the open loop gain is improved from 68 dB to 74 dB and the input referred noise is also reduced from 926 / nV Hz to 475 / nV Hz . This amplifier operates at 0.8 V power supply voltage with a power consumption of 0.9 μW. All the simulations are obtained by using Hspice tool with 0.18 μm CMOS TSMC parameters.


Introduction
In recent years, much effort has been put into the reduction of supply voltage and the supply power of mixed signal CMOS systems [1]. Three main reasons can be given for the advent of low-voltage circuits [2]. As a first reason, since the channel length is scaled down into submicron and gate-oxide thickness is decreased dramatically, in order to ensure the device reliability, the supply voltage has to be reduced. As a second reason, because of increasing number of components implanted on a single chip, the power per electronic function is increased. Since a silicon chip can only dissipate a limited power per unit area, the power consumption has to be lowered. The third reason is dictated by portable and battery-powered equipment. The supply power and the supply voltage have to be reduced to have an acceptable operation period from a battery.
The low noise operational amplifier is one of the most essential parts of analog circuits. In MOSFET devices, there are two important noise sources, which are flicker noise (below 1MHz) and thermal noise [3], [4]. Designing a high dc gain and low noise CMOS OTA with a low supply voltage is very complicated. In this paper by using a simple modification the gain and noise of conventional OTA are improved with the constant power consumption.
The proposed OTA is described in section 2. In section 3 a design procedure is presented. In section 4 proposed circuit has been simulated using the models of the TSMC 0.18 µm technology and a comparison of proposed OTA with conventional one and other configurations is summarized. The paper is concluded in section 5.

Proposed OTA
Circuit schematic of proposed OTA is shown in Fig. 1A, which is indeed a modified version of a conventional OTA shown in Fig. 1B. In this circuit the input signal is applied to transistors M1 to M4. Thus transistors M3 and M4 are not used as an active load anymore. Transistors M7 to M10 are used to improve gain and output signal swing.

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A High-Gain and Low-Noise 0.9 µW Operational Amplifier Fig. 2 shows the current variations versus input differential voltage v i2 -v i1 . It can be observed that the circuit works as a differential amplifier in part of the input signal.
Voltage gain of the proposed OTA is given by: The noise contribution of the second stage of the opamp is negligible, because it is divided by the gain of the previous stage when referred to the input [5]. Also noise contribution of current source is negligible. Thus thermal noise per unit bandwidth [6] produced by transistors is almost given by: Thus input-referred thermal noise Power Spectral Density (PSD) of the proposed OTA and conventional OTA can be written as: Where k is the Boltzmann's constant, T is the temperature in kelvin. The coefficient γ is equal to 2/3 for long channel transistors and it needs to be replaced by a larger value for submicron MOSFETs. It also varies to some extent with the drain-source voltage [3]. Input-referred flicker noise PSD of the proposed OTA and conventional OTA can be shown as (8) and (9) respectively, where C OX is capacitance per unit area of the gate oxide, K fN is NMOS flicker noise coefficient and K fP is PMOS flicker noise coefficient. It can be observed that total input-referred noise in proposed OTA is much smaller than conventional one.
In this work all transistors are biased in weak inversion to have large g m in addition of low power consumption. Since opamps are usually designed to be operated with negative-feedback connection, frequency compensation is necessary for closed-loop stability. The frequency compensation of proposed OTA is easily achieved like the conventional one [7].
The main drawback of this OTA is its limited input signal caused by transistors M3 and M4, which is equal to: Input signal swing is one threshold voltage smaller than conventional OTA, that is because of transistors M3 and M4.
Note that if the output signal is taken from nodes A or B, for ideal current source M5, CMRR is given by: For r o2 = r o4 it is approximated by:

Design Procedure
For g m9 =g m10 and g m1 =g m2 =g m3 =g m4 noise spectral density can be written as: DC gain is also given by:

Simulation Results
The proposed OTA was simulated with the supply voltage of V DD = 0.35 V and V SS = -0.45 V. For the simulations, 0.18 µm CMOS technology parameters were used. The biasing current source was 1 µA. All the devices used have 0.5 µm length (three times the lowest value for the employed topology). The inversion coefficient of transistors is I C1,2 = 0.103 and I C3,4 = 0.256, thus these transistors are in moderate inversion. Table 1 summarizes widths of the transistors used in the proposed circuit. Table 2 summarizes specifications of the circuit resulted from simulations and compares them with the conventional OTA and other configurations. Bode plot of the OTA is shown in Fig. 3. It can be observed that, since the DC gain is increased and bandwidth is constant, the unity gain-bandwidth product is larger than conventional OTA, however, phase margin is decreased. Fig. 4 shows the transient characteristic of the proposed structure with a capacitor load of 10 pF when a square signal of 0.6 V PP at 2 MHz is applied at the input of unity-gain configuration of OTA. The slew rate is 0.8 V/µs which is equal to slew rate of conventional OTA. Fig. 5 shows the equivalent input referred noise, it can be observed that the input referred noise is significantly lower than conventional OTA. Fig. 6 shows the total output noise voltage which is obvious that the proposed OTA has better performance than conventional one. Fig. 7 shows the measured response for a 100 Hz, 20 µV peak-to-peak sinusoidal input voltage. The measured THD was -44 dB. Fig. 8 shows the voltage of nodes A and B for proposed and conventional OTA. It can be observed that the slope of the curve (i.e., the voltage gain) in the proposed OTA is larger than conventional OTA.

Conclusion
A low-voltage and low-power OTA was proposed in this paper, which was modified version of conventional OTA. By using a simple modification, the voltage gain and noise performance were significantly improved, however the CMRR and input signal swing range in comparison to conventional OTA decreased. The simulation results showed that the DC gain is two times larger than conventional OTA and input referred noise is two times lower than conventional one.
To demonstrate the feasibility and scalability of the design a standard 0.18 µm CMOS process with very restrictive supply voltage of 0.8V has been used.