Low-Voltage CMOS Multiplier Circuit Based on the Translinear Principle

In this paper, novel current-mode analog multiplier circuit based on a pair of voltage-translinear Loop is presented. The proposed circuit is designed in 0.18 µm standard CMOS technology. Simulation result using HSPICE that verify the functionality of circuit with 1 V supply is presented. The circuit can find application in the implementation of wide range of analog systems, Fuzzy and Neural Network circuits.


Introduction
Analog circuit design has received wide attention due to the supply voltage scaling down and their potential of lower power consumption [8, 10 from 12] and they are used in the fields of analog signal processing and parallel-computing neural or fuzzy systems. These applications usually require divider/multiplier circuits to cancel non-linearity or to implement modulators or aggregation operators [3][4][5][6].
Several techniques to design CMOS divider/multiplier circuits have been proposed in the literature.The first approach is to use the current-mode square root and squarer circuit based on the square-law characteristics of MOS transistors operated in the saturation region. [3] However, the power consumption by this approach is large; the square circuit requires bias currents for all input signals to make MOS transistors operate in the saturation region. The second approach is to use translinear principle of MOS transistor operated in the saturation or subthreshold region. [1,2] The translinear principle, introduced by Barry Gilbert in 1975 [I], is one of the most important circuit theory contributions in the electronics era. In its original formulation, the translinear principle provides a simple and efficient way to analyze and synthesize nonlinear circuits based on bipolar junction transistors (BJTs). Due to their exponential characteristics, the translinear principle can be extended to MOS transistors operating in saturation. This approach has the advantage of low power consumption.
In this paper we proposed a new low-voltage divider/multiplier circuit based on the properties of translinear loop which is work in saturation region. The proposed circuit work with a single power supply 1V which is lower than previous proposals and make it suitable for low-voltage and portable applications.
Section 2 reviews the properties of translinear loops. The proposed squarer circuit is described in section 3. Section 4 presents the proposed low voltage divider/multiplier and simulation result is presented in section 5. Conclusion is presented in section 6.

Voltage Translinear Loops
Consider, for instance, the circuits of Figs. 1a and 1b. They represent a four-transistor voltage-translinear loop in stacked and up-down topology, respectively, with two MOSFETs connected clockwise and another pair connected counterclockwise. Applying the KVL, the following expression is obtained for both cases: And replacing = ℎ + � 2 and assuming equal MOS transconductance factors and threshold voltages, the following expression is obtained: Hence, several nonlinear current-mode functions can be implemented by properly injecting such currents. For instance, if we force Being I 5 a certain current, after squaring both sides in (3) and rearranging, currents I 1 I 2 and I 5 become related by Therefore, a geometric-mean circuit is obtained if I 1 and I 2 are the input currents and the output current is a copy of I 5 .Alternatively, a squarer/divider is obtained if the output is a copy of I 2 and the inputs are I 1 and I 5 . The simplest way to force (4) is to use the well-known structure of Fig. 2. However, the diode-connected MOSFET of the current mirror precludes very low voltage operation due to the stacking of two diode-connected transistors.

The New Low-Voltage Squarer Circuit
Equation (4) can be alternatively implemented using the novel topology of Fig. 3. Now a FVF, formed by transistors M 1 and M F1 , sets the proper reference dc voltage at the loop nodes. An advantage of this structure is that the source of M 1 is a very low impedance node, so that voltage at this node is kept essentially constant regardless of the input and output current. We have selected V DD =1V in order to have an appreciable voltage swing.

The New Low-Voltage Divider/Multiplier Circuit
Following will described the principal of operation of the proposed Divider/Multiplier. Consider the following expression: It becomes apparent that if we were able to calculate the geometric mean of two currents and then to introduce the output current into a squarer circuit having the following input-output characteristic: Then, according to (8), a current-mode multiplier/divider implementing could be obtained. This idea is shown schematically in Fig. 4, where the geometric-mean and squarer/divider outputs have been assumed to be flowing out.
Low-Voltage CMOS Multiplier Circuit Based on the Translinear Principle  5 shows the proposed low-voltage current-mode divider/multiplier circuit. In this topology, I a is a constant bias current so the output current I OUT will be the multiplication of current I 1 by current I 3 .

Simulation Result
The squarer circuit depicted in Fig.3 and the current multiplier in Fig.5 was laid out in standard 0.18μm CMOS technology. Post layout simulations from extracted circuit were performed for a 1 V single power supply voltage using HSPICE and level 49 parameters (BSIM3V3). Fig.6 shows SPICE simulation of the squarer circuit where a constant DC current is applied as I 1 and a triangular current for I 2 .The result is showed by I OUT .
The DC characteristic of proposed current multiplier is presented in Fig.7 where a constant bias current is applied to the circuit as I 3 .  Table 1 summarizes some relevant result of the multiplier/Divider which proposed previously and compared them to this work. Power Consumption 700 µ W 90 µ W Figure 7. Simulated DC transfer characteristic of the multiplier (Iout as a function of I1 with I3=10u and I2 ranging from 2uA to 10uA in 2uA step)

Conclusions
A new, Low-voltage current Divider/Multiplier circuit based on properties of a translinear loop is described. The proposed circuit works with a single 1V power supply which makes it suitable for designing low-voltage analog processing circuit.